1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of CMOS, BiCMOS, or silicon-germanium BiCMOS semiconductor devices.
2. Related Art
In the manufacture of large scale integration semiconductor devices, several types of devices are fabricated concurrently on the same chip or wafer. For example, in a complementary metal oxide semiconductor (“CMOS”) process both P-channel field effect transistors (“PFET”) and N-channel field effect transistors (“NFET”) are manufactured on the same chip concurrently. A bipolar complementary metal oxide semiconductor (“BiCMOS”) process increases the complexity by adding the concurrent fabrication of bipolar devices—for example, conventional NPN or PNP transistors—to the same chip. By growing a thin silicon-germanium layer as the base of a bipolar transistor on a silicon wafer, a heterojunction bipolar transistor (“HBT”) with improved speed and frequency response can be formed. The addition of silicon-germanium techniques to the BiCMOS process, for example, is referred to as silicon-germanium BiCMOS. In order to form circuits on a chip, various other circuit components such as resistors and capacitors are also formed concurrently on a chip. Using CMOS for an example, resistors are formed concurrently with PFETs and NFETs.
Because devices are formed concurrently on the same chip a process step used in the fabrication of one device may affect the fabrication of other devices. Occasionally extra process steps must be added in order to keep processes required for fabrication of one device from conflicting with the fabrication process of another device on the same chip. Therefore, it is advantageous and desirable to simplify the fabrication process whenever possible by, for example, eliminating steps or finding compatible processes. Simplification of the fabrication process can also provide economic benefits by making the manufacturing process either cheaper or more efficient. As an example, on a CMOS, BiCMOS, or silicon-germanium BiCMOS chip, resistors are typically formed in the same polycrystalline silicon layer used to form the gates of PFETs and NFETs on the same chip.
The value of a resistor is measured in ohms. As known in the art, the value of a resistor is directly proportional to the resistivity of the material comprising the resistor multiplied by the length of the resistor and inversely proportional to the product of the width and depth of the resistor. The resistivity of a material can also be measured by its sheet resistance expressed in ohms per square (because a small square has the same resistance as a larger square of the same thickness). The value of the resistor is then determined by the number of squares comprising the resistor, calculated by dividing the length by the width. On a semiconductor chip, the resistivity of the material comprising the resistor can be readily manipulated by changing the doping of the material.
By way of background, FIG. 1 shows a cross sectional view of various features and components of structure 100 which includes various features and components of a low resistivity resistor and a PFET fabricated on the same wafer. Structure 100 includes polycrystalline silicon layer 102 for a low resistivity resistor. Polycrystalline silicon layer 102 is N+ doped—meaning that it is relatively heavily N type doped. Polycrystalline silicon layer 102 can be doped by implantation or diffusion as known in the art. Polycrystalline silicon layer 102 is typically phosphorous doped with a dose of approximately 5*1015 atoms per square centimeter. The thickness of polycrystalline silicon layer 102 is typically approximately 2,500 Angstroms.
Polycrystalline silicon layer 102 is used to form a resistor by providing silicide contact regions 104 at the ends of polycrystalline silicon layer 102 as shown in FIG. 1. Silicide contact regions 104 provide a means for connecting the resistor formed from polycrystalline silicon layer 102 to other devices on the wafer or to external electrical contacts. Formation of silicide over the entire length of polycrystalline silicon layer 102 is prevented by silicide blocking oxide 106. Silicide blocking oxide 106 is formed before silicide contact regions 104 and can be formed from silicon oxide (SiO2) as known in the art. Polycrystalline silicon layer 102 is formed on field oxide 108. Field oxide 108, 110, and 112 structures are composed of silicon oxide material and are formed in a manner known in the art. Field oxide 108, 110, and 112 provide electrical isolation between devices on silicon substrate 116 in a manner known in the art.
Continuing with structure 100 in FIG. 1, structure 100 includes features and components of other CMOS structures, such as a P-channel field effect transistor, or PFET, on the same wafer as a resistor. Structure 100 includes N well 118 for a PFET. N well 118 is N type single crystal silicon which can be doped by ion implantation in a manner known in the art. Structure 100 further includes source 120 and drain 122 composed of P+ type material—meaning that it is relatively heavily doped P type material —which can be doped in a manner known in the art. Structure 100 also includes gate oxide 124, and gate polycrystalline silicon 126, both formed in a manner known in the art. By the addition of N well 118, source 120, drain 122, gate oxide 124, and gate polycrystalline silicon 126, a PFET is formed on the same wafer as a resistor.
Gate polycrystalline silicon 126 is formed from the same layer as polycrystalline silicon layer 102 and both are doped at the same time. Thus, gate polycrystalline silicon 126 is typically N+doped using phosphorous dopant with a dose of approximately 5*1015 atoms per square centimeter and the thickness of gate polycrystalline silicon 126 is typically approximately 2,500 Angstroms. The doping of gate polycrystalline silicon 126 determines the doping of polycrystalline silicon layer 102. That is, considerations determinative of a desirable value for gate resistivity of approximately 100 ohms per square take precedence over considerations for resistor resistivity. Thus, the value of the resistor is adjusted by adjusting the number of squares in the resistor rather than adjusting the resistivity of the material comprising the resistor.
In summary, FIG. 1 shows that structure 100 includes several features and components used to form a resistor on field oxide 108, while structure 100 simultaneously includes several CMOS features and components such as the PFET between field oxide 110 and field oxide 112. Thus, during the process of fabricating a resistor, several of the features and components for CMOS structures, such as N well 118, source 120, drain 122, gate oxide 124, and gate polycrystalline silicon 126 are present on the same wafer. Hence, the processing steps for forming a resistor are required to be economical and compatible with CMOS processes, i.e. not conflict with or cause undesirable changes in other CMOS structures on the same wafer. Adjustment of constraints and parameters, in particular the resistivity, involved in resistor formation is, therefore, subjugated to the requirements of PFET (or NFET) formation when a resistor is fabricated as illustrated in FIG. 1.
The resistor illustrated in FIG. 1 has a relatively low resistivity of approximately 100 ohms per square, as pointed out above. There are certain advantages to fabricating a resistor with a higher resistivity, for example, temperature coefficient of the resistor, also referred to as “TCR”, can be improved. Simply stated, TCR expresses the change in resistance per degree C. from the resistance value at 25° C. For example, a 1,000 ohm resistor with a TCR of 0.1%/° C. has a value of 1050 ohms at 75° C. A smaller TCR improves the thermal stability of the circuit, i.e. circuit performance is more predictable and dependable despite temperature changes. As another example, reduced variability in resistivity for higher resistivity values can be used to improve the accuracy in fabrication of the resistor value.
Thus, there is need in the art to provide economical and simplified formation of high resistivity resistors in large scale integrated CMOS processes which are compatible with the formation of polycrystalline silicon gates in PFETs and NFETs. Moreover, there is need in the art for fabrication of high resistivity resistors with improved temperature coefficient and more accurate control of resistivity value.